The trend in the semiconductor industry today is the production of ever increasingly more capable semiconductor components, while decreasing component size. Double patterning methods are popular methods to realize increased semiconductor device density. Double patterning methods allow the formation of structures smaller than a current generation's pitch width. With the need to achieve ever smaller feature sizes and thinner feature heights being an ongoing driver, new methodologies are sought.
Positive tone and negative tone double patterning techniques are available for achieving increased semiconductor device density. FIGS. 1A-1C illustrate a cross-sectional view of steps in forming a semiconductor pattern using positive tone double patterning. As illustrated in FIG. 1A, a photoresist layer is patterned into a photoresist pattern 102. The photoresist pattern 102 overlays at least one pattern transfer layer. In one embodiment, as illustrated in FIG. 1A, the photoresist pattern 102 overlays a silicon oxynitride layer 104 and a hard mask layer 106. In another embodiment additional pattern transfer layers are utilized. The hard mask layer 106 is used when etching the final pattern into a final layer 108, such as poly-oxide.
FIG. 1B illustrates the placement of spacers 110 around the edges of the photoresist pattern 102. As illustrated in FIG. 1C, the remaining photoresist 102 is removed, leaving behind the spacer material to form a spacer pattern 110. As further illustrated in FIG. 1C, the spacer pattern is used as a template to etch a final pattern 112 into the hard mask layer 106, that is then used to etch the target layer 108.
FIGS. 2A-2E illustrate a cross-sectional view of steps in forming a semiconductor pattern using negative tone double patterning. Similar to FIGS. 1A and 1B, in FIGS. 2A and 2B, a photoresist layer 202 is formed over a plurality of pattern transfer layers, such as a silicon oxynitride layer 204 and a hard mask layer 206, which are over the target layer 208. As illustrated in FIG. 2B, spacers 210 are placed around the edges of the photoresist pattern 202. As illustrated in FIG. 2C, the remaining photoresist 202 is removed, leaving behind the spacer material to form a spacer pattern 210.
FIG. 2D illustrates the application of a spin-on-carbon (SOC) layer 212 over the spacer pattern 210. In one embodiment, the SOC layer 212 is applied to the entire wafer. As illustrated in FIG. 2E, the spacer pattern 210 is etched away leaving the SOC layer 212 as an SOC pattern layer 212. As further illustrated in FIG. 2E, the SOC pattern layer 212 is etched to form a final pattern 214 that is etched into the target layer 208.
FIG. 3 illustrates a pair of top-down layouts of a semiconductor device comprising a pair of select-gate wordlines and a plurality of core cell wordlines. As illustrated in FIG. 3, when the select-gate wordlines and core cell wordlines are patterned, the spacing between a select-gate wordline and a nearest core cell wordline may vary. This inconsistency in select-gate wordline placement leads to a number of well known difficulties in semiconductor device operation. If the spacing between the select-gate wordlines and the edge core cell wordlines is off, the boosting voltage will be off. Further, a small space from select gate to edge cell will result in interference. The core cell operation, controlled by the two select-gates, is affected by their spacing dimensions to the select gate. Such problems with varying lateral spacing dimensions become more problematic as the pitch continues to diminish. For example, the problem becomes quite severe in 32 nm structures. For example, even small differences in lateral dimensions can result in a select gate being laid so that it overlays the first core cell wordline, effectively resulting in high junction leakage or a dead cell.